Si

Chip Depth Explorer

Package to FinFET gate, six scales

Scale ladder

Heat spreader + TIM PCB, substrate, bumps Metal routing layers

Dielectric insulation Silicon substrate Transistors (fins, gates, S/D) Electron / data flow Labels

Layer separation0%

Clock (visual)1.2 Hz

Gate voltage V_G0.00 V

StateOFF

I_D / fin0

Logic out1

Scroll continuous zoom through every scale · Drag orbit · Click inspect · Double-click dive · [ ] step scale · 1-6 jump · Esc clear

Level 1 · Package

bit 1 bit 0 electrons

ScalePackage

Field of view-

Zoom×1

10 mm